1. Field of the Invention
The present invention relates to a semiconductor memory device, and more specifically, to a single-poly UV-erasable electrically programmable read only memory device or a single-poly one-time programmable (OTP) memory device.
2. Description of the Prior Art
The semiconductor industry has been advanced to the field of Ultra Large Scale Integrated (ULSI) technologies. The fabrication of the nonvolatile memories also follows the trend of the size reduction of a unit device. Thanks to advantages such as non-volatility, fast access time and low power dissipation, non-volatile memory can be applied in portable handy equipments, solid-state camera, PC cards and so on. The nonvolatile memories include various types of devices, such as electrically alterable read only memory (EAROM), and electrically erasable programmable read only memory (EEPROM). Different types of devices have been developed for specific applications. These parts have been developed with a focus on the high endurance and high-speed requirements. EEPROM needs multi-layer of polysilicon and silicon dioxide, therefore, multi-masking are used during the fabrication, thereby increasing the time for manufacturing the devices. One of the present researches is focus on how to integrate the manufacture process to reduce the cost. One of the approaches is to integrate the memory process with the CMOS fabrication. Up to now, many approaches toward to the formation of the EPROM and EEPROM by using one single poly process. In such technique, an indispensable control gate is buried in silicon bulk by ion implantation for capacitively coupling an overlying polysilicon floating gate.
A prior art that relates to the field is U.S. Pat. No. 6,174,759 filed May 3, 1999, by Verhaar et al., entitled “Method of manufacturing a semiconductor device”, assigned to U.S. Philips Corporation (New York, N.Y.). U.S. Pat. No. 6,174,759 disclosed a process that can integrate with the CMOS process. U.S. Pat. No. 6,191,980 filed May 31, 2000, assigned to Lucent Technologies, Inc., discloses a single poly EEPROM. The device includes a control device, a switch device and an erase device, all of which share a common polysilicon floating gate that is designed to retain charge in the programmed memory cell. The memory cell can be safely erased without risking the junction breakdowns. U.S. Pat. No. 6,044,018 filed Jun. 17, 1998, assigned to Mosel Vitelic, Inc. (Hsinchu, T W), entitled “Single-poly flash memory cell for embedded application and related methods”discloses a single poly memory. U.S. Pat. No. 6,044,018 discloses a single-poly flash memory cell manufacturable by a standard CMOS fabrication process. A NMOS floating gate is electrically connected to a PMOS floating gate.
In the article IEEE transaction on electron device, Vol. 37, No. 3, March 1990 p. 675, in which disclosed single poly-Si EEPROM. The structure includes an embedded control gate that is formed by ion implantation. The cell includes separated transistor and coupled capacitor and can be manufacturable by standard CMOS process. The further technique that can be compatible with the CMOS can be found in IEEE JOURNAL OF SOLID STATE CIRCUITS, Vol. 29, No. 3, 1994, p. 311. The structure includes NMOS and PMOS, the inversion layer under the PMOS gate and p+ doped region act as the control gate. When positive voltage applies to the p+ doped region, the voltage level of the floating gate determines the capacitance ratio of the NMOS and PMOS. The art may be formed by standard CMOS process. The structure refers to SIPPOS (single poly pure CMOS).
FIG. 1 shows the layout of prior single poly non-volatile memory, the structure includes n+ doped region under the floating gate and buried in the substrate. The structure occupies too much area. FIG. 2 shows another type of layer according to the prior art. The structure is consisted of a capacitor and a PMOS. The technique has to provide space for forming the capacitor.